Non-volatile memory (NVM) devices are able to retain stored data even when the power supply is interrupted. NVM devices can be programmed using electrical signals. For the embedded memory device to be byte-operational, a two-transistor (2T) cell structure which includes a memory transistor such as silicon-oxide-nitride-oxide-silicon (SONOS) type and a select or access transistor in series can be provided. The memory transistor stores data programmed into the memory cell while the access transistor selects the memory cell to be programmed or erased. However, 2T cell structure requires a lot of space. Split gate NVM devices are proposed to offer a high density solution which requires less space, low cost, re-programmable in system, and highly reliable.
However, the 2T cell structure and current split gate NVM devices suffer several limitations, such as scalability issues or program disturbance. Further, there is also a desire to form split gate memory devices which can be integrated together with other types of devices, such as low voltage (LV), medium voltage (MV) and high voltage (HV) devices, to form embedded memory in a cost effective manner. As such, it is desirable to provide a split gate NVM cell with improved scalability, increased program/erase speed, minimized program disturbance and with improved endurance and a low cost methodology which can integrate logic and memory devices on the same chip.